Teaching a model the intuition of an analog designer

The hardest part of analog design lives in the heads of a shrinking pool of experts. Here's how we think about capturing that tacit knowledge in an AI system.

The bottleneck in analog design was never raw computation. Simulators have been fast for years. The bottleneck is judgement — the sequence of decisions a designer makes between reading a specification and arriving at a circuit that meets it. Our whole approach starts from treating that judgement as something a model can learn.

Design as a sequence of decisions

A good analog designer moves through a problem in recognisable steps: pick a topology that suits the spec, size the devices to hit the targets, add the bias and compensation that keep it stable, then check it against the corners of the real world. Each step is a decision informed by thousands of prior designs. We model it as exactly that — a mapping from intent to architecture to a sized, simulatable netlist.

The verification loop is the ground truth

A model that proposes circuits is only useful if those circuits actually work. So the simulator sits at the centre of everything. The model proposes; SPICE disposes. AC, DC and transient sweeps across process corners tell us whether a candidate meets its spec, and that signal feeds straight back into the loop. The model doesn't get to be confidently wrong — the physics has the final say.

What makes it hold together

Three things matter more than anything else. First, grounding in the constraints of real Process Design Kits, so the output is manufacturable rather than merely plausible. Second, learning from verified designs, so the intuition being captured is the kind that survives contact with silicon. Third, keeping a human designer in the loop — the goal is to amplify expert engineers, not to pretend they aren't needed.

Still early

We are at the beginning of this, and we hold our claims to the standard the field deserves. But the trajectory is clear: the intuition that took a career to build can increasingly be encoded, applied, and verified in a fraction of the time. That is what we are building, one verified schematic at a time.

— The Samurai Team